module UART_Sender(
	oTX,
	iSTART,
	iDATA,
	iCLK,
	iRST_N,
	oBUSY
);

output oTX, oBUSY;
input iSTART, iCLK, iRST_N;
input [31:0] iDATA;

assign oTX = tx_data[0];
assign oBUSY = busy;

reg[7:0] baudcnt;
reg clock;
always@(posedge iCLK) begin
	baudcnt <= baudcnt + 8'd1;
	if(baudcnt == 8'd217)begin 
		clock <= ~clock;
		baudcnt <= 8'd0;
	end
end

reg busy, prev_start;
reg [39:0] tx_data;
reg [5:0] bitcnt;
always@(posedge clock or negedge iRST_N)begin
	if(!iRST_N) begin
		busy <= 1'b0;
		prev_start <= iSTART;
		tx_data <= 39'd1;
		bitcnt <= 41;
	end
	else begin
		prev_start <= iSTART;
		if(({prev_start, iSTART} == 2'b01) && !busy) begin
			busy <= 1'b1;
			tx_data <= {1'b1, iDATA[31:24], 2'b01, iDATA[23:16], 2'b01, iDATA[15:8], 2'b01, iDATA[7:0], 1'b0};
			bitcnt <= 6'd0;		
		end
		else if(busy)	begin
			if(bitcnt < 6'd40) begin
				bitcnt <= bitcnt + 1'd1;
				tx_data <= {1'b1, tx_data[39:1]};
			end
			else busy <= 1'b0;		
		end
	end
end

endmodule
	